1. Field of the Invention
This invention relates to high speed and low cost memory subsystems for synchronous dynamic random access memory (SDRAM). The invention is particularly directed to controlling the layout of high capacity SDRAM memory modules and the positioning of associated electronics in light of a known signal rise time to avoid problems related to transmission line effects.
2. Description of Related Art
Synchronous dynamic random access memory offers a significant increase in speed over conventional dynamic random access memory (DRAM). SDRAM memory often operates at speeds above 66 MHz and 100 MHz or faster SDRAM systems are expected to become widely used. This increase in speed, however, creates a new set of problems for memory subsystem design as transmission line effects become more important.
In any memory system, it is important to maintain the signal integrity of the address, control and clock signals, however, this is particularly difficult at the high speeds of SDRAM systems as transmission line effects begin to appear. To avoid transmission line reflections in SDRAM subsystems, a solution has been proposed requiring the use of series resistors, such as thin film buried resistors. This solution also requires resistive/capacitive termination, e.g. AC termination, at both ends of the wiring. This is a relatively complex and expensive solution to the problem. Furthermore, the resulting signals may still be poor to marginally acceptable at some points in the system.
Another approach to maintaining high quality signals in high speed SDRAM systems involves the use of specially designed buses and interfaces. However, this approach is also relatively complex and costly.
Yet another difficulty with high capacity SDRAM relates to the numerous address lines needed for the amount of memory to be accessed. For example, newer high capacity SDRAM is typically mounted in dual in-line memory modules (DIMMs) having 168 or 200 pins, although single in-line memory module (SIMM) implementations are also used. SDRAM also uses a few additional signals not needed for conventional DRAM, such as the clock signal. This adds to the number of connections that must be made in the memory subsystem.
The large number of required connections in modern SDRAM/DIMM systems requires space for the interconnecting wiring, which in prior memory subsystems has resulted in long distances between the SDRAM memory and components such as memory controllers, the clock and multiplexers. This causes problems with signal reflection due to the length of the wiring involved. The numerous connections and distances between the memory and the associated memory subsystem components of prior designs has resulted in long parallel wiring nets which creates many difficulties with cross coupling between the wiring, particularly when multiple banks of memory are used.
The problem of laying out the wiring for the large number of connections in an SDRAM system is doubled when a dual memory bank design is selected as compared to a single bank design. Some implementations of SDRAM systems have offered only a single bank of memory modules. A single bank design is simpler to design and produce, but offers less flexibility and performance than a dual bank design.
The present invention provides an SDRAM memory subsystem suitable for use with at least eight DIMMs of SDRAM high speed memory organized into two banks. The invention operates well at speeds up to at least 100 MHz and also allows complete compatibility with conventional DRAM DIMMs or SIMMs. Further, the present design is relatively inexpensive as compared to previously proposed solutions to the layout and transmission line problems. It may use the same DIMM connectors and motherboards as more conventional DRAM memory subsystem designs and does not require thin film buried series resistors on the DIMM for the data nets.
The layout and configuration of the wiring and support electronics in the memory subsystem of the present invention reduce the coupled noise between the large number of parallel data nets which has plagued prior implementations of dual bank designs.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an SDRAM memory subsystem which is low cost and which does not require the use of series resistors.
Still another object of the present invention is to provide an SDRAM memory subsystem which does not suffer from poor signals due to transmission line effects.
It is another object of the present invention to provide an SDRAM memory subsystem design which offers a dual bank design with at least eight SDRAM DIMMs.
A further object of the invention is to reduce coupled noise in a multiple memory bank design.
It is yet another object of the present invention to provide a memory subsystem which may be used interchangeably with high speed SDRAM/DIMMs and more conventional DRAM memory.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.